Sigrity SystemSI technology addresses high-speed design challenges with comprehensive chip-to-chip signal integrity (SI) analysis solutions. SystemSI is available in two configurations: SystemSI Parallel Bus Analysis targets source-synchronous designs, and SystemSI Serial Link Analysis focuses on projects with SerDes channels. SystemSI includes a block-based schematic editor to make it easy to get started with very basic data. As design work progresses, models are swapped in to reflect the detail of design structures. SystemSI includes frequency domain, time domain, and statistical analysis methods to ensure robust parallel bus and serial link interface implementations.
SystemSI Parallel Bus Analysis
This end-to-end analysis solution targets source-synchronous parallel interfaces such as designs with DDRx memory. Pre-layout capabilities (including an optional via wizard) enable work to begin with models that are quickly generated and connected. As the design is refined, more detailed models are swapped in to reflect actual hardware behavior. Concurrent simulation accounts for the effects of dielectric and conductor losses, reflections, inter-symbol interference (ISI), crosstalk, and simultaneous switching noise. These simulations are able to fully account for impacts associated with non-ideal power delivery system characteristics. Graphical outputs and post-processing options give designers insight that enables rapid system improvements.
SystemSI Serial Link Analysis
This award-winning chip-to-chip analysis solution focuses on high-speed SerDes designs such as PCIe, HDMI, SFP+, Xaui, Infiniband, SAS, SATA, USB, and more. It makes early assessments using basic templates. Support for industry-standard IBIS AMI transmitter and receiver models enable simulations of channel behavior for serial links with chips from multiple suppliers. Chip model developers have access to techniques that assist them in model development. Models of multiple packages, connectors, and boards can be added to reflect the entire channel. Simulations identify crosstalk issues and show the effectiveness of chip-level clock and data recovery (CDR) techniques. Full-channel simulations including millions of bits of data confirm overall bit-error rate (BER) to determine if jitter and noise levels are within specified tolerances.
- Fast and precise simulations for designs at frequencies that range from DC to 10+ gigahertz
- Accurate handling of non-ideal power delivery system influences on SI, which can be the dominant cause of reliability problems
- Easy-to-use graphic editor including a novel net-based, block-wise schematic editor
- Proven S-parameter handling to ensure accurate system-level time domain simulations
- Related Cadence® tools support model extraction, tuning, conversion, and hook-up
- SPICE subcircuit-based modeling approach supporting common formats such as IBIS, HSPICE, Touchstone, BNP, and MCP
- Highly automated measurement and reporting capabilities
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