XJ Developer guides you step by step through the test setup for JTAG and non-JTAG components. You can read in net lists from one or several pcb's and interconnect them. After having attributed the PWR and GND signals you assign to each JTAG compatible component a BSDL (Baundary Scan Description File) and generate so a JTAG chain. The BSDL files you can get at no charge from your component manufacturer. With the JTAG chain also non-JTAG component can be included in the test now.
After the setup a DFT Testcoverage report can be created. This is possible before routing or production of the pcb. A list of the untested nets can be exportet to OrCAD Capture so that test points can be assigned to these nets.
In the XJDeveloper you verify the pin assignment of your JTAG connector for the test with XJLink2. Afterward you can select the tests you want to do:
- Chain Integrity Test
- Connection Test
- Switch Test
- Memory Test
- LED Test