With one click on the problem area in the evaluation, the vue zooms in the layout exactely to the area where the cause of the problem in the layout can be seen. A possible cause for the impedance discontinuity could be an interruption in the correspondent reference layer for the return flow.
On standardised interfaces the number of vias on the address bus or data bus should be equal too. Differences in the number of vias for such busses are detected and displayed.
At differential signals will also be analyzed whether the two lines are in phase. It will also be indicated via a graphic on which area on the line the signals move away from the phase and it can be zoomed per click in the layout.
To start with an analysis for Electrical Rule Checks in OrCAD Sigrity ERC an average preparation time of only 2 minutes is required. There are no simulation models required. The analysis will take depending on the complexity of the circuit board approximately 10-20 minutes.
As a result, clear graphical reports are issued, from which you can derive clear work instructions.
In the following example the graphical report for impedances of selected lines is displayed. On the lines the impedances for different sections are variably colored.
By clicking on the graphic the tool jumps and zooms into the layout and shows the respective position in the layout. Also in the layout the color codes on the lines are visible for the impedances. Together with the view of the reference layers the causes can so be determined at the position.