OrCAD FPGA System Planner

When FPGAs are used on printed circuits, the FPGA designer begins much earlier with the programming of the algorithms than the PCB designer, who shall do the routing on the interconnect device. Because the FPGA designer has no information about the later physical placement at the beginning of his work, he uses the pins by chance and only according to electrical properties. If later, after the placement, the connectivities have a lot of crossings, this would not only mean more work for the PCB designer but also eventually cause additional layers in the PCB. The information that a pin swap is desired reaches the FPGA designer so late and can result in many modifications in the source code.

OrCAD Capture

OrCAD FPGA System Planner is a tool which is used at the beginning of a development process. By an approximate placing on the drawing surface with the FPGAs, which represent their mesurements, a quick setting of the important componants is possible. Afterwards the busses like DDR3, PCI Express,... can be assigned easily. The FPGA System Planner consists of very detailed informations about the internal construction of FPGAs. Therefore the busses can only be assigend to the correct pins in the correspondant bases. Now a pin synthesis can be started and in doing so all connectivities are optimized, that a pin assignment with preferably intersection-free connectivities is selected. 

The FPGA designer can take per UCF, QSF,... or .CSV the pin assignment. The tool generates automatically the schematic symbol and the footprint with the correspondant pin names.

If there are still enquiries for a pin swapping during the layout, it is possible to manage this by the OrCAD FPGA System Planner.

 
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