Digital circuits contain signals and composite signal sequences which must be fully synchronized to each other. Internal and conducted signal propagation lines and different clock frequencies in a design complicate a manual timing prediction. TimingDesigner is an analysing tool that enables to present an analyze critical timings of a design in timing diagrams. Especially for circuits containing multiple components such as controllers, memory and FPGAs, the tolerance of the signals can be very small and must be precisely planned.
In inter-dependent signal sequences, a static timing analysis can help in the specification, analysis and implementation of timing. With TimingDesigner alternative signal sequences can quickly be compared and by worst-case analyses optimal solutions be prepared. The specifications intuitively determined can be clearly documented in the form of tables and diagrams.
Violations of the timing are difficult to localize. In the software special cause and effect mecanisms are integrated which show the conclusions on the causes of the problem areas and provide precise optimization of timing.