Stress Analysis and Stress Limitation with CARE PCB
In the past it was possible to achieve high reliability with simplicity and a large stock of materials. Such a strategy would be - under consideration of economic aspects - unthinkable for products nowadays. Essentially the reliability of a device is defined during the design phase and the early development phase. During the phases of construction and insertion it is no longer possible to obtain a correction of the reliability in the products. That is why it is necessary to resort to measures for the protection of reliability in an early stage of development.
These measures comprehend:
- The use of qualified components
- A systematic search of the weaknesses of reliability and elimination of weak points
CARE® PCB can analyze and optimize easily and effectively the safe operation of your product. CARE is a tool for calculating reliability which represents all possible errors and their effects on the layout/system behavior. Using CARE it is possible to develop more reliable systems for the profitable hardware by reducing the development cycle and development time. Critical areas are detected early. This way we can find and eliminate faults already during the design phase, this means before the layout. In order to design high-availability systems CARE indicates the optimum hardware configuration that is required to get the highest availability at minimal hardware cost.
By integrating in your available design environment and the connection to all common CAD/CAE systems, PCB CARE offers virtually "on the fly" a declaration of all potential design défaults and their effects on reliability.
The modules for reliability calculation are:
- MTBF (Mean Time Between Failure)
- MRS (Mechanical Reliability Simulation)
- Stress Calculator
- SDTA (Stress De-rating & Thermal Analysis)
- FMEA (Failure Mode Effects Analysis)
- FMECA (Failure Mode Effects & Criticality Analysis)
- TA (Testability Analyse)
- FTA (Fault/Event Tree Analysis)
- MTTR (Mean Time to Repair)
- RBD (Relaibitiy Block Diagramm)