Allegro Global Route Environment

If in the Allegro PCB Designer the signal nets were merged as bundles to functional groupes, these bundles can be used for further planning of the routing. With the Allegro PCB Design Planning Option two further planning steps can be done: Plan Spatial and Plan Topological. In the Global Route Environment (GRE) also the Delay Tuning and the transformation in copper is possible with the final step. Given that all planned steps are preserved as intelligent airwires in the design data, planning steps forward and backward are possible and the total result can be iterativly improved. In the Delay Tuning different parameters can be specified so that the result is as close as possible to a manual routing result.  


  • Route around Etch Shapes
  • Disable Compression During Plan Accurate
  • Allow or Prohibit Tuning in Constraint Regions
  • Embedded Component Support
  • Performance and Quality Improvements

Allegro Global Route Environment GUI
In the GRE surface settings can be made if: 
  • (1) the routing shall be done around the copper surfaces           
  • (2) a Delay in Constraint Regions is enabled                                
  • (3) the compression is disabled while Plan Accurate

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