Allegro PCB High-Speed Option

With the High-Speed Option Constraint Manager is extended by many electrical design rules and their online testing in PCB Editor. Here all rules are displayed that are required for the design of modern high-speed interfaces such as: DDR2, DDR3, DDR4, PCI Express and USB 3.0. A typical rule is for example the dynamic phase control on which an inidcated phase shift on differential pairs must be compensated by bumps in the shorter line of the differential pair within a defined area. The rule violation of the dynamic phase compensation is displayed in real time as color-coded numerical value in Constraint Manager and as DRC violation in PCB Editor.

High-Speed Bunmp bei differentiellen Paaren



The video shows that different lenghts of a differential pair can lead to a phase shift. This is demonstrated with Timing Vision and afterwards selectively compensated with the function Auto interactive Phase Tune (AIPT):

If on an existing PCB layout the corners of a line are optimized subsequently, so you can do this with the function AICC Autointeractive Convert Corner. Choose 90°, 45° or Arc with any radii and after a click all corners are adjusted.

High-speed nets and differential pairs have various design rules which have to be observed. To place systematically the lines and to pay attention tightly focussed to the rules, Timing Vision is your assistant. A new kind to visualize rules and interdependences to ohter nets.

To extend the existing Constraint Manager rules can also be defined using formulas and thereby accessed date of the design (e.g. real routed length).

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