Before the first line of the code is programmed, 3 experts (FPGA, schematic and layout) have the possibility to preplan approximately the layout. Given that the physical dimensions of the FPGAs are displayed on the drawing surface, a placement of the FPGAs and the connected big components can be realized. By simple assignment of interfaces (e.g. DDR2, PCI Express) numerious signals can be assigned and partial netlists can be created.
In the Allegro FPGA System Planner models for each FPGA are stocked to know how the internal pinout is and how caracteristics each pin has. With this informations an optimisation synthesis can be done to make sure that there are as few intersections of netlist connections as possbile. If now the FPGA programmer uses this reasonable pinout this will be a huge advantage which leads to easier designs and eventually less of layers in the PCB layer structure. As additional advantage the schematic developer gets a schematic in the OrCAD/Allegro format (including schematic symbols) and the layouter a placement (.brd) with the footprints and aire wires (rats).