Net Scheduling or setting the sequence of the interfaces of a net is useful, to define topologies of nets. A net with several connected components is internaly partitionned in point-to-point connections of a defined sequence. Subsequently you can assign design rules to the subnets. With a Dasy Chain or FlyBy topology a sequence 1,2,3,4,... is defined. This is used e.g. on DDR3. If a DDR2 memory structure is defined, there are also branches with rules. These rules describe that the branches of a network must have the same lenght. But also on low-speed circuits for e.g. a power supply it can be very useful. A current of 20 amperes flows from 1 to 2, from 2 to 3 only of 3 amperes and from 3 to 4 the voltage drop is measured by a sense rule-line. After the net scheduling also the conducter width can be defined as design rule corresponding to the maximum amperage.
With the assembly of components on curcuit boards there are different minimum distances which are given by the placement machines. These minimum distances can be defined in the Constraint Manager. In the definition there are two different values, depending on the sort of component (e.g. SMD, BGA,...) and the layout of the components fitted next to each other. During the placement the minimum distance is displayed as circle and at the same time the cursor located component snaps on to this value. In doing so components can be placed extremely dense and all placement specifications of the assembler can be held.
If designs are complex it is no longer possible to obtain straightaway an optimal component placement. The solution is the previous planning of a routing. Therefore the function Flow Planner Interconnect gives support. Nets can be defined for bundles and so be combined into logical units. A bundle shows the minimum width for a routing, because it adds the conductor width and the required condutor distance of all signals in the bundle and displays it as a wide line. Bundles can be placed on a board very easily. By this intermediate level of reference lines (bundles), it is possible to indicate the connexion of signals with their size ratio during the routing. Using this technology it is easy to plan a routing in advance, as the layouter assigns the signals already on the layers. With this information of the bundles it is possible to make at the same time the placement of components and routing channels and finally to optimize the size ratio of a circuit board. Bundles describe the design intent and can also be on or hidden while or after the routing. Bundles remain in the data base and the design intent is available also for later redesigns.
Miniaturisation mostly requires an optimized integration of circuit boards in mechanical housings. The previous formates (DXF and IDF) for the exchange of eCAD and mCAD data have limits. For that reason the pro-step consortium, consisting of many EDA and mCAD manufacturers and users of different industries, agreed on the definition of a new standard EDMD (.ifx). Allegro PCB Designer supports this new format for an incremental and documented data exchange.