The Power Aware Signal Integrity solution can be used for memory modules (e.g. DDR3) or for multi gigabit serial link interfaces (e.g. PCI Express). Thereby algorithmic transceiver models are supported. The simulation methods rely on 3D full wave field solvers. The patented calculation methods enable exact results already after a short time of caculation which enable exact prognoses about bit error rates (BER) too. The results of the power integrity analysis have sign-off quality. Coupled differential signals and nets passing across discrete components (x-nets), are dedected, extracted and analyzed automatically. Allegro Sigrity SI decodes electrical structures of several involved nets. The simulation can be done from the schematic respectevely the PCB Editor and the results are memorized in the common data base.