Validate serial links are compliant with industry standards (PCIe). The need for speed (faster data throughput) requires more attention be paid to each section of the interface. Transceivers require advanced modeling techniques to support dynamic equalization and clock and data recovery algorithms. 3D package models must be used to accurately characterize interconnect from the die to the package pin. PCB structures must be carefully characterized such that signal loss, frequency dependant materials, and impedance discontinuities are all accurately represented through industry leading extraction technology. Allegro Sigrity Serial Link SI is addressing the challenges associated with serial link design. Industry-leading interconnect extraction technology provides an accurate and uniquely integrated solution for channel modeling, including non-ideal power effects. Robust frequency and time domain simulation technology is combined with statistical techniques for advanced multi-gigabit channel analysis. Industry-leading IBIS-AMI modeling expertise enables advanced channel simulation with algorithmic equalization modeling (ex. FFE, DFE, ...) Automated eye diagram and bathtub generation for Bit Error Rate (BER) analysis. Provides a comprehensive environment for design and accurate assessment of high speed serial links to ensure robust IC package and PCB implementations Sweep Manager.