Allegro Sigrity Power Aware SI Option

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Allegro Sigrity Power-Aware SI addresses the challenges associated with source synchronous bus design. Industry-leading interconnect extraction and power-aware IBIS modeling technology includes the non-ideal power and ground effects. Concurrent simulation of signal, power, and ground accurately determine Setup and Hold margins. Comprehensive, automated JEDEC-based measurements and post-processing. Easy-to-use environment featuring popular memory interface compliance kits is highly integrated with layout, allowing engineers to efficiently close on memory interface timing. Reflections, Xtalk, SSO Simulated Together.

Allegro Sigrity Power Aware SI Option

Automatic Setup & Hold Derating Slew rates measured on each cycle. Derating factor is pulled from table Applied to setup/hold margins each cycle 
Automation

Raw waveforms measured like a virtual oscilloscope. Tabulated reports for: Waveform quality Eye, quality Setup & hold Delays & skews Criteria plots, waveforms, eye diagrams all linked to HTML reports

Allegro Sigrity Power Aware SI Option enthält folgende Basismodule der Sigrity Technologie:

  • SIGR011 Broadband SPICE
  • SIGR021 T2B
  • SIGR031 CAD Translators
  • SIGR301 PowerSI
  • SIGR311 3D-EM
  • SIGR400 SPEED2000
  • SIGR556 SystemSI I PBA II

 

 

Übersicht über die Allegro Sigrity Produkte:

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