In a QIR (Quarterly Incremental Release), customer under maintenance will be provided several new features in this "interim release". The current QIR (from Hotfix 17.2.025) offers new features that enhance productivity again.
All customers under maintenance can download the update for free. Full documentation is available in the Download of this update.
The new features are:
For PCB designs, design for manufacturing flow has traditionally consisted of creating fabrication data at the end of the design, which is then sent to the fabricator. Hours, or days later, the fabricator sends back a list of issues to be addressed. The issues are corrected, and the cycle of data creation is repeated, resulting in lost days in the design to fabrication phase.
Realizing this time delay between the design center and fabrication, design centers create an internal sign-off group to shorten the manufacturing cycle by bringing fabrication validation tools into their own environment . This process reduces the data to manufacturing cycle time, but not necessarily the number of cycles between the tools. Fabrication data still needs to be generated and imported into the validation tool, and a list of issues is returned to the designer for correction. This current model is, more aptly, named verify for manufacturing.
Each iteration of this process costs time in the release to manufacturing phase, and also impacts the schedule of the next design that is interrupted to correct the issues on the previous design.
In-Design DFx in PCB Editor improves the process even further by putting fabrication checks into the constraint management system of PCB Editor. Manufacturing issues realized during the editing process can immediately be corrected rather than waiting for hours, or days, without generating manufacturing data and sorting through a list of violations from another tool. The sign-off phase still exists using tools, such as the Allegro®/OrCAD® Manufacturing Option, but with In-Design DFx, the iterations and the time required to produce fabrication data decreases multiple times.
Figure 1: In-Design DFF Checks in Analysis Modes
Figure 2: Trace to outline violation
Constraint Manager contains a new Manufacturing worksheet, which is divided into two categories, DFF CSet and Design. You define a CSet in the DFF CSet and assign to stackup layers in the Design category. Each Manufacturing Design for fabrication category consists of five major subcategories:
The layout editors now include an advanced tool that enhances the ability to locate, review, and address DRCs. The DRC Browser UI contains various navigation, sorting, and filtering capabilities making it easier to focus on resolving design issues by DRC violation types and areas. The DRC Browser provides feedback on the number of errors, including bar and pie charts that are dynamically updated as issues are corrected or introduced, while editing the design.
Abbildung 3: DRC Browser Features
Figure 4: Filter options
The MCAD Collaboration environment streamlines the ECAD/MCAD flow for IDX, reducing the concern for managing the multiple changes and modifications that occur during the design cycle. This environment is based on a shared repository where both the layout editor and MCAD tools read and write IDX files.
Allegro Integrated Analysis and Checking is a new, unique environment blending the best of Allegro and Sigrity technologies that provides analysis and checking capability entirely within the PCB Editor framework. For rule checking, DRC and ERC capabilities continue to depend on Constraint Manager as the single cockpit.
This release introduces two new workflow analysis capabilities for impedance and coupling. The workflows provide guided access to Sigrity analysis with results returned as dockable tables and plots, or as new Vision overlays.
Figure 5: Sigrity Workflow in Allegro PCB Editor
There have been changes to the way differential pair members are checked by the Allegro constraint system. At times standard design rules do not apply to the members of a differential pair which requires them to be checked differently from non-differential pairs. Enhancements have been made to the way Static Phase is calculated. It now includes via transitions when checking back to Driven Pins and specific spacing constraints, to control the minimum spacing between the vias of the members of a differential pair.
The dynamic component alignment behavior with snapping guidelines is similar to Microsoft programs such as PowerPoint. Designers can perform the one-two combination of placing and aligning components real time increasing their productivity and efficiency. Available during the Move command, the guidelines can be configured for either component origins, place bound edges, or both. You can also select, color of choice for the lines indicating the available snap points. This setting is located in the Color dialog Display folder.
Figure 6: Dynamic Component Alignment
The following list of features have also been enhanced in different areas of the layout editors.
In release 17.2-2016 QIR 3, new functionality was introduced into the Padstack Editor to allow the import and export of padstack data using an XML format (.pxml). In QIR 4, it is now possible to process multiple padstack definitions from within a single file using the -x option.
This is the fourth phase of major 3D improvements planned for the new 3D Canvas with many additional features under development.
Figure 7: fourth phase of major 3D improvements
3D Canvas functionality delivered in different releases are:
The main enhancements made to 3D Canvas in this release (Phase IV) are:
Figure 8: Cutting Plane (Cross Section) Views in PCB Editor
Full documentation is available in the Download of this update.