Timing Designer

TimingDesigner® is the industry standard tool for interface timing design. It provides an easy to use and intuitive method for defining and analyzing interface timing requirements. TimingDesigner can generate SDC timing constraints from a timing diagram. This enables users to visually define design requirements and then automatically generate SDC to drive place and route.

SDC is an open source industry standard timing constraint format supported by most FPGA and ASIC design flows. Allowing users to generate SDC constraint files from a timing diagram reduces the complexity of the SDC constraint format while providing users a visual verification that their constraints are specifying the desired design intent.

The initial release of TimingDesigner with SDC support focuses on the Altera® FPGA design flow. As a result of this integration, customers can leverage the graphical timing analysis features of TimingDesigner to rapidly develop their SDC timing constraints for Altera devices, with the overall system requirements in mind.

Benefits:

• Enables users to take advantage of powerful features in the SDC constraint format without having to learn all the nuances of writing SDC
• TimingDesigner allows users to easily incorporate timing delays and requirements for all components in the interface, enabling a system level view of timing
• While using TimingDesigner to generate SDC constraints users are also automatically developing documentation to describe interface timing requirements and design intent