What's new in PSpice

Version 17.2-2016 [05/2016]

• Hardware in the Loop Simulation
• Design Difference Viewer
• Advanced Annotation
• Demo Design Browser
• ISCF Export
• XML Export/Import
• PDF Export
• New Models (TNY274-80, PC457, HCPL-M453, PS8101, GTO)
• PSpice DMI Template Code Generator
• Miscellaneous Enhancements
  • Support for TCL 8.6
  • New Delay Functions for Behavorial Simulation Models
  • New Flag Option for .OPTIONS command
  • Support for Negative Values in Hyteresis Voltage and Threshold voltage
• New Website www.PSpice.com
• TI Workbench based on PSpice
  

Version 16.6 Quarterly Intermediate Release QIR#9 [06/2015]

• New Chapters in Learning PSpice
• New Simulation Macro Models for the Capture-PSpice Flow
• VBIC Support Added in PSpice
• New Device Added in PSpice for the Device Model Interface Support
• ADMS XML Filters for Verilog-A to PSpice DMI Models Translation
• Documentation Enhancements 
  • PSpice Device Modeling Interface API Reference Guide
  • PSpice Device and System Modeling with C/C++ and SystemC
• PSpice Lite License String Added for PSpice Lite Mode

Version 16.6 Quarterly Intermediate Release QIR#8 [12/2014]

• Iteration count for each time step in transient analysis
• Enhancements in PSpice Component Menu
  • LED with reverse leakage current, breakdown voltage, maximum power dissipation, forward current
  • Voltage and Current Noise Sources (DC Noise, Sine Noise, Pulse Noise, Exponential Noise, Random Noise)
• Analyses Using PSpice added in Learning PSpice
  • Introduction
  • Transient Analysis
  • AC Analysis

Version 16.6 Quarterly Intermediate Release QIR#7 [09/2014]

• System C Support
• Enhancements in the Object Distribution Feature
• Enhancements in Learning PSpice
• Enhancements in Custom Design Rule Checker
• Hysteresis Core Loss Calculator
• PSpice Report
• PSpice Performance Upgrade
• Design Entry HDL power symbols support in the DE HDL-AMS Simulator flow
• PSpice Part Search Symbol Viewer
• Enhancement: Pin Names and Pin Numbers Behaviour on Part Rotation
• Enhancement: Specify Pin Spacing in New Part from Spreadsheet using INI Options
• Enhancement in .OPTIONS command
• Rapid PSpice Model Association
• New PSpice Modeling Apps
  • Voltage Controlled Oscillator (VCO)
  • Transient Voltage Suppressor (TVS)
  • Switches
  • PWL Source
  • Independent Sources
• Redefined Quick Place Menu
• Monte Carlo Temperature Sweep
• Random Functions for PSpice Engine
• Mechanical Parts in Capture - Allegro Flow
• Enhancements in Display Properties dialog box
• Enhancement in Comment Text
• Capture Viewer
• Capture - Sigrity SI flow
• Miscellaneous Enhancements:
  • Object Alignment and Distribution in OrCAD Capture
  • Enhancements in Place Part
  • Expression support in .TRAN, .OPTIONS, and .FOUR
  • Parameter support in .PROBE command
  • New Convergence options in .OPTIONS command
  • TCL Functions support in circuit file
  • Ignore DML check in IBIS2Spice
• Global Parasitic Support
• Frequency Response Analysis
• Documentation Enhancements
• Advanced Analog Options:
  • Shunt Capacitance (CSHUNT)
  • Diode Ohmic Resistance (DIODERS)
  • Diode Junction Capacitance (DIODECJO)
  • Alternate Path Search (TRANCONV)
  • Debugging Convergence Failure (CONVAID)
  • Bipolar Junction Transistor (BJT) Capacitance (BJTCJ)
• PSpice Modeling Apps
  • New productivity applications for PSpice simulation:
    • Independent Sources
    • Zener Diode
    • RF Inductor
• Parameter-driven dialog to automatically create symbol and model
• Parameters editable on the fly
• OrCAD Capture Text Justification
• PSpice Convergence Updates:
  • Pseuodotran added to auto-convergence profile
  • TimeStep backtracking
  • CSHUNT Option
  • Parasitics
  • ENVTOL
• New OrCAD Tcl APIs:
  • Ability to define customer variables in TitleBlock for different variants
  • Option to turn off NetGroup Aware Aliases display
  • Tcl option to set Incremental Annotation update for all projects
    • Can be used at a site installation
• Customize Monte Carlo distribution
• Access to get/set project libraries
• Miscellaneous:
  • Move pin name / pin number in Part Editor
  • Model indexing for shared environment
  • Design DATE formats
  • Capini Manager app support update for 16.6 release
  • Cross-geo multi-site library update support
  • Monte Carlo shows all available results even on convergence failure
  • Convert Views supported in Allegro PCB net listing

Version 16.6 Quarterly Intermediate Release QIR#5 [01/2014]

• New random functions
  • RND function
  • RNDR function
  • RNDC function

Version 16.6 Quarterly Intermediate Release QIR#4 [10/2013]

• Expression support in .TRAN, .OPTIONS, and .FOUR commands
• Parameter support in .PROBE command
• New Convergence options in .OPTIONS command
  • PREORDERMODE option
  • MINSIMPTS option
  • RMIN option
  • BPPseudoTran option
  • TRANCONV1 option
• TCL Functions support in circuit file
  • .TCLPOSTRUN command
• Ignore DML check in IBIS2Spice
• Global Parasitic Support
• Enhancements in Learning PSpice
• Frequency Response Analysis
• Documentation Enhancements
  • New Tutorial: Simulating an SMPS Design using Capture-PSpice Flow
  • Reorganization of Content: Co-Simulation using PSpice SLPS Interface

Version 16.6 Quarterly Intermediate Release QIR#3 [07/2013]

• Windows 8 support
• PSpice Modeling Apps
  • New productivity applications for PSpice simulation
    • Independent Sources
    • Zener Diode
    • RF Inductor
  • Parameter-driven dialog to automatically create symbol and model
  • Parameters editable on the fly
• OrCAD Capture Text Justification
• PSpice Convergence Updates
  • Pseuodotran added to auto-convergence profile
  • TimeStep backtracking
  • CSHUNT Option
  • Parasitics
  • ENVTOL
• New OrCAD TCL APIs
  • Ability to define customer variables in TitleBlock for differentvariants
  • Option to turn off NetGroup Aware Aliases display
  • Tcl option to set Incremental Annotationupdate for all projects
    • Can be used at a site installation
  • Customize Monte Carlo distribution
  • Access to get/set project libraries
• Miscellaneous
  • Move pin name / pin number in Part Editor
  • Model indexing for shared environment
  • Design DATE formats
  • Capini Manager app support update for 16.6 release
  • Cross-geo multi-site library update support
  • Monte Carlo shows all available results even onconvergence failure
  • Convert Views supported in Allegro PCB netlisting

Version 16.6 [11/2012]

•  What's new in PSpice Version 16.6
• Learning PSpice Tutorials
• Quick Place Menu
• What If Analysis
• PSpice Simulation Engine Options
  • Multi Threading (speed improvement)
  • Convergence improvements
  • Accuracy improvements
  • Bias Point Convergence
  • Transient Convergence
  • Limit
  • 64-bit Probe data
  • VT Tables
• IBIS Import
• AES Encryption (256 bit)
• Modelle:
  • Schottky diodes
  • Bridge rectifiers
  • High-speed diodes
  • Zener diodes
  • New ferrite material cores
  • Step-up controller
  • Step-down controller
  • LED driver
  • Power management ICs
  • IGBT modules

Version 16.5 [06/2011]

•  What's new in PSpice Version 16.5
• PSpice Testbench in OrCAD Capture
• Modelle:
  • Ladungspumpe (Charge Pump)
  • PWM controller
  • Voltage Mode Control
  • Optokoppler
  • Batterie
  • Solid State Relay
  • Supervisory IC
  • More Vendor Models (Operationsverstärker)
  • SimuLink PSpice Multi-Block Co-Simulation

Version 16.3 [11/2009]

•  What's new in PSpice Version 16.3
• Ease of Use in PSpice probe
• Probe look and feel enhancements
• Probe Customization
• Directly open probe.dat-file
• Enhanced cursor support
• Design templates
• New PWM models and vendor libraries
• Filters
  • Low Pass Filter (Capacitive and Inductive LPF)
  • High Pass Filter (Capacitive and Inductive HPF)
  • Band Pass Filter (Capacitive and Inductive BPF)
  • Band Stop Filter
  • Resonant Filter (Parallel LC BPF Parallel LC BSF Series LC BPF Series LC BSF)
• BJT Amplifiers (bipolar junction transistor)
  • Common Emitter (CE) BJT Amplifiers
  • Common Collector (CC) BJT Amplifiers
  • Common Base (CB) BJT Amplifiers
• Basic Electronics Circuits
  • Op-Amp based differentiator and integrator
• Clipper circuits
  • Negative peak clipper
  • Symmetrical clipper
• Clamper circuits
  • Positive peak clamper
  • Negative peak clamper
• Zener diode circuits
  • Voltage regulator
  • Voltage clipper
• Voltage Multipliers
  • Half wave voltage doubler
  • Full wave voltage doubler
• DC-DC Converters
  • Buck
  • Boost
  • Buck-Boost
  • Flyback
  • Single switch forward converter
  • Double switch forward converter
• Design Templates Digital Circuits
  • Counters
  • Shift Register
  • Synchronous PWM buck controllers
  • High Speed PWM controller
  • Full bridge PWMcontrollers
• Models:
• Analog Devices:
  • 213 models for low quiescent current, CMOS linear regulators
• Taiwan Semiconductor
  • 74 Models of zener voltage regulators
• Fagor
  • 37 models of glass passivated zener diodes

Version 16.2 [06/2008]

• GUI-Update for new Allegro Style
• Usability
• BSIM4 Transistor Model
• Temperature Support in B-devices
• Checkpoint Restart enabled for Mixed Signal Designs
• Smoke enhancements to support new devices
• New model libraries
• State Average Models
• DEHDL/AMS improvements
• Models:
  • ABM for Digital Primitive
  • LOGIC Gate OptoCouplers
  • Precision Voltage Reference
  • Surface Mount Zener Voltage Regulator
  • Low Dropout Adjustable Regulator LM2941
  • Gate Turn Off Thyristor (GTO)
  • Precision Isolation Amplifier
  • Dual High Side MOSFET Driver
  • 8-bit Shift Register CD4094BC
  • ARINC-429 drivers
• Microsemi: Bidirectional suppressor
• On-Semi: Microprocessor supervisor circuit
• Epcos: Surface Mount Power Inductor
• Siliconix: Power MosFET
• NXP: Power MosFET
• STM: High precision rail to rail operational amplifier
• PWM Models:
  • Step-Up/Down/Inverting Switching Regulators
  • High performance fixed frequency power switching regulators
  • Synchronous Voltage-Mode PWM Controller

Version 16.0 [08/2007]

• Improved Convergence
• Auto convergence
• Improved calculating speed (power electronics)
• Simulation restart after time step
• 410 new models (LEDs & Power electronics)

Version 15.7 [07/2006]

• Model Encryption (IP protection)
• Improved Documentation Interface
• New WindowsXP Look and Feel
• New Libraries
• 2000 new vendor models to 46.000
• (IRF, Vishay Siliconix, Coilcraft)

Version 10.5 Service Pack1 [03/2006]

• Enhancement Magnetic Parts Editor
• New Libraries
• 700 new vendor models to 44.000

Version 10.5 [12/2005]

• Modeling
  • Advanced Behavioural Modeling (floor, break, ceil,…)
  • Assertions (warning, error)
  • European Notation (e.g. 2.2k -> 2k2)
  • Model Import Wizard
  • Magnetic Parts Editor
  • New Libraries
  • 1500 new vendor models to 43.300
  • Spice_elem, function
  • New Models
  • Mextram 504
  • Enhanced BSIM
  • Battery model

Version 10.3 [09/2005]

• MonteCarlo History Support
• Importing waveforms in Probe (*.txt, *.csv,..)
• SLPS / Simulink-PSpice-CoSimulation
• New Models
• TOM3
• Enhanced BSIM
• Battery models
• 100 New vendor models to 41.800